Using Design-Level Scan to Improve Design Observability and Controllability for Functional Verification of FPGAs
نویسندگان
چکیده
منابع مشابه
Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification
This paper describes a structured technique for providing full observability and controllability for functionally debugging FPGA designs in hardware, capabilities which are currently not available otherwise. Similar in concept to flip-flop scan chains for VLSI, our design-level scan technique includes all FPGA flip-flops and RAMs in a serial scan chain using FPGA logic rather than transistor lo...
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